Cache memories, which are common random access memories (RAMs) operable at high frequency, are used in computer systems to enhance data processing efficiency; they are accessible by central processing units (CPUs) more than general memories (e.g., dynamic RAMs). Data frequently accessed by CPUs are stored in the cache memories in order to save data (or signal) transmission times.
A CPU directly accesses a cache memory without using a data-conveying device such as an external memory management unit. As a result, the cache memory is usually positioned at a place physically adjacent to the CPU in order to shorten signal transmission times. An operating feature of a data RAM, including cache memories, in a microprocessor (e.g., ‘Alpha AXP 21064 Microprocessor’) has been disclosed at pp. 380˜383 of “Computer Architecture a Quantitative Approach” published by Morgan Kaufman Publishers Inc., in 1996, and written by David A. Paterners and John L. Hennessy.
FIG. 1 shows a typical form of hierarchical memory composition. A processor (e.g., CPU) 1 obtains desirable data by accessing a primary cache (first-level cache or L1) 2, a secondary cache (second-level cache or L2) 3, and a main memory 4, in sequence. Since the secondary cache 3 is accessed by the processor 1 later than the primary cache 2, the composition shown in FIG. 1 is disadvantageous in increasing the number of bits or in enhancing latency performance thereof.
FIG. 2 illustrates another hierarchical memory architecture which has the capability of simultaneous access of a main memory and a secondary cache. A CPU 20 is connected to a main memory 10 through a system bus 50, and to a secondary cache 40 through a processor bus 60. The architecture shown in FIG. 2 is advantageous to extend the number of bits transferred because the CPU can access the main memory 10 and the secondary cache 40 simultaneously, and to improve a latency condition because the secondary cache 40 is utilized as a backup memory for a primary cache (or L1 cache) 30.
However, since data stored in the primary cache 30 are not always present in the secondary cache 40, a procedure must be performed to check whether or not data assigned to the primary cache 30 are present in the secondary cache 40 before removing the data from the primary cache 30. Therefore, logical composition for data replacement becomes complicated.
There has been proposed a set-associative cache memory in which memory locations are segmented into a plurality of groups or banks in order to increase a hit rate therein. The groups or the banks are also called sets or ways.
A recent trend of semiconductor manufacturing processes has been promoted to integrate a secondary cache on a microprocessor chip as well as a primary cache. In the case of embedding a secondary cache in a microprocessor chip together with a primary cache, it is possible to enhance overall performance of a chip because of a prominent increase in the number of data bits accessible between the secondary cache and the microprocessor chip. Nevertheless, hit rate may be reduced because the embedded secondary cache sizes up to an areal limit contrary to an external one. While changes are being implemented to increase the number of sets in the set-associative cache memory in order to compensate for the degraded hit rate due to the reduced size of the embedded secondary cache on the microprocessor chip, increasing the number of sets causes block replacement logic to be complicated and circuit area to be large.